Memory chip test equipment system program description

With the rapid development of the component industry, the memory chip test equipment has also made great progress. So, how much do users know about the memory chip test equipment?

In order to simplify the test steps, reduce the complexity of the test, improve the test efficiency, and reduce the test cost, the memory chip test device realizes the convenient and quick test of all the above memory chips under the same platform. The memory chip test device realizes the accurate operation of accessing various memory read/write timings based on the external bus by appropriately adjusting the external bus timing according to the unique read/write timing access characteristics of the above various memories.

The memory chip test equipment 40-bit NAND FLASH and NIOSII are bridged by ABUS (FPGA) to completely convert the timing of the external bus into the operation timing of NAND FLASH. The 40-bit NAND FLASH chip is composed of five independent 8-bit NAND FLASH chips. The external IO ports of the five 8-bit devices are spliced into 40-bit external IO ports, and the respective control lines (NCLE, NALE, NRE, NWE) are connected together to form a set of control lines (NCLE, NALE, NRE, NWE). The chip selects are independently derived into NCS0-NCS9, and the busy signals are independently derived as R/B0-R/B9. The memory chip test equipment SRM module and NIOSII are connected through ABUS to achieve correct timing read and write operations. During the test, only 8 bits were tested at a time, and all the space tests were completed in 5 times.

The memory chip test equipment is developed using the LNEYA refrigeration heating temperature control advantage. The high configuration parameters in terms of performance are more conducive to the operation of the memory chip test equipment.

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